1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com tc1550 features 500v breakdown voltage independent n- and p-channels electrically isolated n- and p-channels low input capacitance fast switching speeds free from secondary breakdowns low input and output leakage applications high voltage pulsers ampli?ers buffers piezoelectric transducer drivers general purpose line drivers ? ? ? ? ? ? ? ? ? ? ? ? general description the supertex tc1550 consists of a high voltage n-channel and p-channel mosfet in an 8-lead soic package. this is an enhancement-mode (normally-off) transistor utilizing an advanced vertical dmos structure and supertexs well-proven silicon-gate manufacturing process. this combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coef?cient inherent in mos devices. characteristic of all mos structures, this device is free from thermal runaway and thermally induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. n- and p-channel enhancement-mode dual mosfet -g indicates package is rohs compliant (green) absolute maximum ratings parameter value drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55c to + 150c soldering temperature * 300c device package option bv dss /bv dgs r ds(on) (max) 8-lead soic 4.90x3.90mm body 1.75mm height (max) 1.27mm pitch n-channel (v) p-channel (v) n-channel () p-channel () tc1550 TC1550TG-G 500 -500 60 125 pin con?guration ordering information gp sp gn sn dp dp dn dn product marking yy = year sealed ww = week sealed l = lot number = green packaging yyww c155 0 l l l l 8-lead soic (tg) (top view) absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. * distance of 1.6mm from case for 10 seconds. 8-lead soic (tg)
2 tc1550 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com sym parameter min typ max units conditions bv dss drain-to-source breakdown voltage 500 - - v v gs = 0v, i d = 1.0ma v gs(th) gate threshold voltage 2.0 - 4.0 v v gs = v ds , i d =1.0ma v gs(th) change in v gs(th) with temperature - -3.8 -5.0 mv/ o c v gs = v ds , i d = 1.0ma i gss gate body leakage current - - 100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current - - 10 a v gs = 0v, v ds = max rating - - 1.0 ma v ds = 0.8 max rating, v gs = 0v, t a = 125c i d(on) on-state drain current - 100 - ma v gs = 5.0v, v ds = 25v 150 350 - v gs = 10v, v ds = 25v r ds(on) static drain-to-source on-state resistance - 45 - v gs = 5.0v, i d = 50ma - 40 60 v gs = 10v, i d = 50ma r ds(on) change in r ds(on) with temperature - 1.0 1.7 %/ o c v gs = 10v, i d = 50ma g fs forward transconductance 50 100 - mmho v ds = 25v, i d =50ma c iss input capacitance - 45 55 pf v gs = 0v, v ds = 25v, f = 1.0mhz c oss common source output capacitance - 8.0 10 c rss reverse transfer capacitance - 2.0 5.0 t d(on) turn-on delay time - - 10 ns v dd = 25v, i d = 150ma, r gen = 25 t r rise time - - 15 t d(off) turn-off delay time - - 10 t f fall time - - 10 v sd diode forward voltage drop - 0.8 - v v gs = 0v, i sd = 500ma t rr reverse recovery time - 300 - ns v gs = 0v, i sd = 500ma n-channel switching waveforms and test circuit r ge n inpu t puls e generato r v dd r l d.u.t. output 10v 0v 0v v dd t d( off) inpu t output t r t f t d( on ) t (on) t (off ) 10% 90 % 90 % 10 % 90 % 10 % n-channel electrical characteristics (t a = 25c unless otherwise speci?ed) notes: all dc parameters 100% tested at 25c unless otherwise stated. (pulsed test: 300s pulse at 2% duty cycle.) all ac parameters sample tested. 1. 2.
3 tc1550 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com p-channel switching waveforms and test circuit r ge n inpu t puls e generato r v dd r l d.u.t. output 0v -10v 0v v dd t d( off) inpu t output t r t f t d( on ) t (o n ) t (off ) 90 % 10 % 90 % 10 % 10 % 90 % sym parameter min typ max units conditions bv dss drain-to-source breakdown voltage -500 - - v v gs = 0v, i d = -1.0ma v gs(th) gate threshold voltage -2.0 - -4.5 v v gs = v ds , i d = -1.0ma v gs(th) change in v gs(th) with temperature - 3.5 6.0 mv/ o c v gs = v ds , i d = -1.0ma i gss gate body leakage current - - 100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current - - -10 a v gs = 0v, v ds = max rating - - -1.0 ma v ds = 0.8 max rating, v gs = 0v, t a = 125c i d(on) on-state drain current - -90 - ma v gs = -5.0v, v ds = -25v -100 -240 - v gs = -10v, v ds = -25v r ds(on) static drain-to-source on-state resistance - 85 - v gs = -5.0v, i d = -5.0ma - 80 125 v gs = -10v, i d = -10ma r ds(on) change in r ds(on) with temperature - 0.85 - %/ o c v gs = -10v, i d = -10ma g fs forward transconductance 25 40 - mmho v ds = -25v, i d = -10ma c iss input capacitance - 40 70 pf v gs = 0v, v ds = -25v, f = 1.0mhz c oss common source output capacitance - 10 20 c rss reverse transfer capacitance - 3.0 10 t d(on) turn-on delay time - 5.0 10 ns v dd = -25v, i d = -100ma, r gen = 25 t r rise time - 8.0 10 t d(off) turn-off delay time - 8.0 15 t f fall time - 5.0 16 v sd diode forward voltage drop - -0.8 -1.5 v v gs = 0v, i sd = -100ma t rr reverse recovery time - 200 - ns v gs = 0v, i sd = -100ma p-channel electrical characteristics (t a = 25c unless otherwise speci?ed) notes: all dc parameters 100% tested at 25c unless otherwise stated. (pulsed test: 300s pulse at 2% duty cycle.) all ac parameters sample tested. 1. 2.
4 tc1550 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www .supertex.com typical application circuit v dd 2 v h v dd 1 supertex md1213k 6 v l v ss 2 v ss 1 gnd outa outb ina inb oe 0.47f +12v 3.3v cmos logic input s supertex tc1550t g +250 v -250 v piezoelectri c transducer 10n f 250v 10n f 250v 15v 15v block diagram sn gn sp gp 1 2 3 4 dp dp dn dn 6 7 8 5 n-channel p-channel
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such appl ications unless it receives an adequate product liability indemnification insurance agreement. supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry and specifications are subject to change without notice. for the latest product specifications refer to the supertex inc. website: http//www .supertex.com . ?2008 all rights reserved. unauthorized use or reproduction is prohibited . 1235 bordeaux drive, sunnyvale, ca 9408 9 te l: 408-222-8888 www .supertex.com 5 tc1550 (the package drawing(s) in this data sheet may not re?ect the most current speci?cations. for the latest package outline information go to http://www.supertex.com/packaging.htm l .) doc.# dsfp-tc1550 a091608 8-lead soic (narrow body) package outline (tg) 4.90x3.90mm body, 1.75mm height (max), 1.27mm pitch 1 8 seating plane gauge plane l l1 l2 e e1 d e b a a2 a1 seating plane a a to p v iew side v iew vi ew b vi ew b 1 note 1 (index area d/2 x e1/2) vi ew a-a h h note 1 symbol a a1 a2 b d e e1 e h l l1 l2 1 dimension (mm) min 1.35* 0.10 1.25 0.31 4.80* 5.80* 3.80* 1.27 bsc 0.25 0.40 1.04 ref 0.25 bsc 0 o 5 o nom - - - - 4.90 6.00 3.90 - - - - max 1.75 0.25 1.65* 0.51 5.00* 6.20* 4.00* 0.50 1.27 8 o 15 o jedec registration ms-012, variation aa, issue e, sept. 2005. * this dimension is not speci?ed in the original jedec drawing. the value listed is for reference only. drawings are not to scale. supertex doc. #: dspd-8solgtg, version g090808. note: this chamfer feature is optional. if it is not present, then a pin 1 identi?er must be located in the index area indicated. the pin 1 identi?er can be: a molded mark/identi?er; an embedded metal marker; or a printed indicator. 1.
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